A. Technical Field
The present invention relates generally to wired OR functions in array computations and more specifically to a low power wired OR circuit.
B. Background of the Invention
Content addressable memory (CAM) devices, boundary addressable memory (BAM) devices and priority resolution circuits all incorporate wired OR functions. In the CAM circuit, a match circuit employs a wired OR horizontal result line. In the BAM circuit, xe2x80x9cgreater thanxe2x80x9d and xe2x80x9cless thanxe2x80x9d circuits both employ a wired OR signal line (greater than line and less than line respectively). Wired OR functions contribute substantially to power dissipation and speed limitations.
Referring now to FIG. 1, there is shown a prior art wired OR circuit 100. Wired OR circuit 100 comprises a plurality of logic blocks 102. Each logic block 102 is coupled to a driver circuit 113 to receive an input signal. Each logic block 102 comprises a logic circuit (not shown) for pulling a wired OR signal line 108 low in response to certain conditions. Pre-charge circuit 104 is used for pre-charging the wired OR line 108 to a high voltage from ground 106. When asserting a signal on the wired OR signal line 108, each logic block 102 draws current from wired OR 108 line until wired OR line 108 is fully discharged to ground 106. One disadvantage of this setup is that it creates a high voltage swing on wired OR 108 line, thereby providing high power dissipation.
Furthermore, relative switching speed of wired OR line 108 is not controllable since there may be one to all the logic blocks 102 pulling line 108 low. For example, when many logic blocks 102 pull down wired OR line 108, wired OR line 108 discharges to ground 106 almost instantly. In such a case, the transition speed of line 108 is very fast. Conversely, when only one logic block 102 pulls wired OR line 108 down, the transition speed of line 108 is slow and the wired OR 108 does not discharge to ground 106 as fast when only a single logic block is pulling signal line 108 low. The variation in transition time makes it very difficult to implement circuits that limit the voltage swing as well as to limit the power consumed by wired OR signal line 108.
Accordingly, there is a need for a circuit that limits power dissipation and has a predictable transition speed. It is also desirable to have an electrical circuit that is not prone to electrical noise.
The present invention overcomes the deficiencies and limitations of the prior art with a low power wired logic circuit that reduces voltage swing on a wired OR signal line. A low power wired OR circuit in one embodiment of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR line, thereby reducing power dissipation in the wired OR circuit.
Low power wired OR circuit further comprises a common current return line coupled to each individual logic block to connect each block to common current source. Running current through a common current source to ground rather than directly to ground advantageously allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.